CLAIM CONSTRUCTION MEMORANDUM OPINION AND ORDER
Claim Construction D
The Parties’ Positions
Plaintiff submits: The plain meanings of these terms do not require that execution of instructions be stopped. Such a limitation is expressed in other claims and should not be read into Claims 1, 10, or 16 of the ’627 Patent. Further, while the terms require that clocks to the processing unit be “shut down,” other clocks may still operate and be received by the processing unit. Dkt. No. 48 at 22–23.
In addition to the claims themselves, Plaintiff cites the following extrinsic evidence to support its position: Carbonell Decl. ¶ 63 (Plaintiff’s Ex. E, Dkt. No. 48-6 at 24–25); Thornton Decl. ¶¶ 87–88 (Plaintiff’s Ex. F, Dkt. No. 48-7 at 34–36).
Defendant responds: See the Changing-the-Frequency-While-Execution-of-Instructions-is-Stopped Terms addressed above.
Plaintiff replies: Neither the ’627 Patent nor the prosecution history justify requiring shutting down the “core clock” or ceasing the execution of instructions. Dkt. No. 53 at 12.
Analysis
There are three issues in dispute. First, whether the processor “clocks” shut down in the claims necessarily include the “core clock.” They do. Second, whether shutting down the processor clock necessarily means that there are no instructions executed. It does not. Third, whether the clock is necessarily stopped for the entire time the frequency is changed. It is not.
The “clocks” of the claims at issue, Claims 1, 10, and 16 of the ’627 Patent, include the core clock. Claim 1 of the ’627 Patent recites:
a frequency generator configured to receive a first clock signal from a clock generator and to adjust a frequency of said first clock signal to furnish clock signals at different frequencies to said processing unit and said second component … wherein, in response to initiating a change in frequency for said processing unit, said processing unit is configured to start a counter and to shut down clocks to said processing unit and said second component.
Claim 10 similarly recites:
said frequency generator configured to adjust said frequency of said first clock signal to concurrently furnish clock signals at different frequencies to said processing unit and said second component … wherein, in response to initiating said change in frequency, said processing unit is configured to start a counter and to shut down clocks to said processing unit and said second component.
Claim 16 similarly recites:
a first clock signal at a first frequency to provide a second clock signal at a second frequency to a processing unit … in response to initiation of a change in frequency for said processing unit, starting a counter and stopping said first and second clock signals.
That is, the “clocks” or “clock signals” of the claims expressly include the processing-unit clock. As explained above, the processing-unit clock is the core clock. See also, ’061 Patent col.3 ll.20–26; ’061 Patent File Wrapper, August 3, 2004 Response at 16–17, Dkt. No. 50-12 at 17–18.
While, as set forth above, the Court understands that execution of instructions during a voltage change requires operation of the core clock, it does not understand the claims at issue here to preclude instructions based on other clocks. As set forth above, the patentee explained during prosecution of the ’061 Patent that execution of instructions during the voltage change means clocking instructions through the processor and that this is not possible when the processor clock is not running. ’061 Patent File Wrapper, August 3, 2004 Response at 16–17, Dkt. No. 50 12 at 17–18. Thus, claimed execution of instructions during the voltage change requires operation of the core clock. The claims at issue here, however, do not refer to either continuing to execute instructions or stopping the execution of instructions, during a voltage change or otherwise. Nor do the claims, which are open-ended, preclude the use or presence of unrecited clocks. Ultimately, the Court finds nothing in the intrinsic record to require that any and all instructions be executed only through use of the core clock. While the Court also finds no intrinsic-record disclosure of using any clock other than the core clock to execute instructions, whether such is technically possible is an issue of fact outside the patents and whether a claim to such undisclosed clock is supported by the disclosure of the Asserted Patents is an issue of invalidity under the enablement or written-description requirements, not an issue of claim construction. Phillips v. AWH Corp., 415 F.3d 1303, 1327 (Fed. Cir. 2005) (en banc) (“we have certainly not endorsed a regime in which validity analysis is a regular component of claim construction”).
The terms at issue do not require that the clocks are necessarily shut down for the entire frequency-change operation. The claims themselves recite when the shut-down clocks are reenabled. For instance, Claim 10 recites:
processing unit configured to register a value corresponding to an amount of time allowed for phase-locked-loop (PLL) circuitry to lock in response to a change in frequency of said first clock signal … a frequency generator coupled to said clock generator and comprising said PLL circuitry, said frequency generator configured to adjust said frequency of said first clock signal to concurrently furnish clock signals at different frequencies to said processing unit and said second component … in response to initiating said change in frequency, said processing unit is configured to start a counter and to shut down clocks to said processing unit and second component … in response to said counter reaching said value, said processing unit is configured to tum on said clocks.
The claim expressly recites that the clocks are shut down for a sufficient period of time to allow the phase-locked-loop circuitry to lock in in response to a change in frequency. Claims 1 and 16 are different. Claim 1 recites: “in response to said counter reaching a specified value, said processing unit is configured to turn on said clocks.” Claim 16 recites: “in response to said counter reaching a specified value, restarting said first and second clock signals.” Unlike Claim 10, Claims 1 and 16 are silent on how or whether the “specified value” is related to the duration of the frequency change. While the Court finds no intrinsic-record disclosure of a specified value other than one “used to measure the time allowed for the phase-lock-loop circuitry to lock to the new frequency,” ’061 Patent col.6 ll.63–66, whether the disclosure of the Asserted Patents supports a claim to such is an issue of invalidity under the enablement or written-description requirements, not an issue of claim construction. Ultimately, the Court finds nothing in the intrinsic record that mandates the clocks be shut down for the entirety of the frequency change.
Accordingly, the Court rejects Defendant’s proposals to limit the claims to prohibit execution of instructions other than those enabled by the core clock and to limit the claims to prohibit an enabled core clock at any point during a frequency-change operation. The Court hereby construes the “clock signal” terms as set forth below, and holds that the shutting-down-the-clocks-in-response-to-a-frequency-change-initiation terms otherwise have their plain and ordinary meaning without the need for further construction:
• In Claims 1 and 10 of the ’627 Patent, “in response to initiating [a/said] change in frequency … shut down clocks to said processing unit and said second component” means “in response to initiating [a/said] change in frequency … shut down clocks, including the core clock, to said processing unit and said second component”; and
• In Claim 16 of the ’627 Patent, “in response to initiation of a change in frequency for said processing unit … stopping said first and second clock signals” means “in response to initiation of a change in frequency for said processing unit … stopping said first and second clock signals, including the core clock.”
Case No. 2:18-cv-00192