Semcon IP v. Amazon.com, Inc.

CLAIM CONSTRUCTION MEMORANDUM OPINION AND ORDER

Claim Construction D

The Parties’ Positions

Plaintiff submits: The plain meanings of these terms do not require that execution of instructions be stopped. Such a limitation is expressed in other claims and should not be read into Claims 1, 10, or 16 of the ’627 Patent. Further, while the terms require that clocks to the processing unit be “shut down,” other clocks may still operate and be received by the processing unit. Dkt. No. 48 at 22–23.

In addition to the claims themselves, Plaintiff cites the following extrinsic evidence to support its position: Carbonell Decl. ¶ 63 (Plaintiff’s Ex. E, Dkt. No. 48-6 at 24–25); Thornton Decl. ¶¶ 87–88 (Plaintiff’s Ex. F, Dkt. No. 48-7 at 34–36).

Defendant responds: See the Changing-the-Frequency-While-Execution-of-Instructions-is-Stopped Terms addressed above.

Plaintiff replies: Neither the ’627 Patent nor the prosecution history justify requiring shutting down the “core clock” or ceasing the execution of instructions. Dkt. No. 53 at 12.

Analysis

There are three issues in dispute. First, whether the processor “clocks” shut down in the claims necessarily include the “core clock.” They do. Second, whether shutting down the processor clock necessarily means that there are no instructions executed. It does not. Third, whether the clock is necessarily stopped for the entire time the frequency is changed. It is not.

The “clocks” of the claims at issue, Claims 1, 10, and 16 of the ’627 Patent, include the core clock. Claim 1 of the ’627 Patent recites:

a frequency generator configured to receive a first clock signal from a clock generator and to adjust a frequency of said first clock signal to furnish clock signals at different frequencies to said processing unit and said second component … wherein, in response to initiating a change in frequency for said processing unit, said processing unit is configured to start a counter and to shut down clocks to said processing unit and said second component.

Claim 10 similarly recites:

said frequency generator configured to adjust said frequency of said first clock signal to concurrently furnish clock signals at different frequencies to said processing unit and said second component … wherein, in response to initiating said change in frequency, said processing unit is configured to start a counter and to shut down clocks to said processing unit and said second component.

Claim 16 similarly recites:

a first clock signal at a first frequency to provide a second clock signal at a second frequency to a processing unit … in response to initiation of a change in frequency for said processing unit, starting a counter and stopping said first and second clock signals.

That is, the “clocks” or “clock signals” of the claims expressly include the processing-unit clock. As explained above, the processing-unit clock is the core clock. See also, ’061 Patent col.3 ll.20–26; ’061 Patent File Wrapper, August 3, 2004 Response at 16–17, Dkt. No. 50-12 at 17–18.

While, as set forth above, the Court understands that execution of instructions during a voltage change requires operation of the core clock, it does not understand the claims at issue here to preclude instructions based on other clocks. As set forth above, the patentee explained during prosecution of the ’061 Patent that execution of instructions during the voltage change means clocking instructions through the processor and that this is not possible when the processor clock is not running. ’061 Patent File Wrapper, August 3, 2004 Response at 16–17, Dkt. No. 50 12 at 17–18. Thus, claimed execution of instructions during the voltage change requires operation of the core clock. The claims at issue here, however, do not refer to either continuing to execute instructions or stopping the execution of instructions, during a voltage change or otherwise. Nor do the claims, which are open-ended, preclude the use or presence of unrecited clocks. Ultimately, the Court finds nothing in the intrinsic record to require that any and all instructions be executed only through use of the core clock. While the Court also finds no intrinsic-record disclosure of using any clock other than the core clock to execute instructions, whether such is technically possible is an issue of fact outside the patents and whether a claim to such undisclosed clock is supported by the disclosure of the Asserted Patents is an issue of invalidity under the enablement or written-description requirements, not an issue of claim construction. Phillips v. AWH Corp., 415 F.3d 1303, 1327 (Fed. Cir. 2005) (en banc) (“we have certainly not endorsed a regime in which validity analysis is a regular component of claim construction”).

The terms at issue do not require that the clocks are necessarily shut down for the entire frequency-change operation. The claims themselves recite when the shut-down clocks are reenabled. For instance, Claim 10 recites:

processing unit configured to register a value corresponding to an amount of time allowed for phase-locked-loop (PLL) circuitry to lock in response to a change in frequency of said first clock signal … a frequency generator coupled to said clock generator and comprising said PLL circuitry, said frequency generator configured to adjust said frequency of said first clock signal to concurrently furnish clock signals at different frequencies to said processing unit and said second component … in response to initiating said change in frequency, said processing unit is configured to start a counter and to shut down clocks to said processing unit and second component … in response to said counter reaching said value, said processing unit is configured to tum on said clocks.

The claim expressly recites that the clocks are shut down for a sufficient period of time to allow the phase-locked-loop circuitry to lock in in response to a change in frequency. Claims 1 and 16 are different. Claim 1 recites: “in response to said counter reaching a specified value, said processing unit is configured to turn on said clocks.” Claim 16 recites: “in response to said counter reaching a specified value, restarting said first and second clock signals.” Unlike Claim 10, Claims 1 and 16 are silent on how or whether the “specified value” is related to the duration of the frequency change. While the Court finds no intrinsic-record disclosure of a specified value other than one “used to measure the time allowed for the phase-lock-loop circuitry to lock to the new frequency,” ’061 Patent col.6 ll.63–66, whether the disclosure of the Asserted Patents supports a claim to such is an issue of invalidity under the enablement or written-description requirements, not an issue of claim construction. Ultimately, the Court finds nothing in the intrinsic record that mandates the clocks be shut down for the entirety of the frequency change.

Accordingly, the Court rejects Defendant’s proposals to limit the claims to prohibit execution of instructions other than those enabled by the core clock and to limit the claims to prohibit an enabled core clock at any point during a frequency-change operation. The Court hereby construes the “clock signal” terms as set forth below, and holds that the shutting-down-the-clocks-in-response-to-a-frequency-change-initiation terms otherwise have their plain and ordinary meaning without the need for further construction:

• In Claims 1 and 10 of the ’627 Patent, “in response to initiating [a/said] change in frequency … shut down clocks to said processing unit and said second component” means “in response to initiating [a/said] change in frequency … shut down clocks, including the core clock, to said processing unit and said second component”; and

• In Claim 16 of the ’627 Patent, “in response to initiation of a change in frequency for said processing unit … stopping said first and second clock signals” means “in response to initiation of a change in frequency for said processing unit … stopping said first and second clock signals, including the core clock.”

Case No. 2:18-cv-00192

Semcon IP v. Amazon.com, Inc.

CLAIM CONSTRUCTION MEMORANDUM OPINION AND ORDER

Claim Construction C

The Parties’ Positions

Plaintiff submits: These terms are not limited to require either stopping the core clock or cessation of execution of instructions at all times while the frequency is changing. With respect to stopping the core clock, dependent Claim 6 of the ’708 Patent expressly requires “shutting down said clock.” This means that the frequency change recited in Claim 1, from which Claim 6 depends, does not require shutting down the clock.With respect to whether the claims allow for a frequency change while executing instructions, the claims are open ended and it would be improper to read such a negative limitation into a positive requirement for frequency change while execution is stopped. Dkt. No. 48 at 21–22.

In addition to the claims themselves, Plaintiff cites the following extrinsic evidence to support its position: Carbonell Decl. ¶¶ 61–65 (Plaintiff’s Ex. E, Dkt. No. 48-6 at 24–25).

Defendant responds: The intrinsic record is clear that the core clock and execution of instructions are both stopped for a frequency change. As explained in the Asserted Patents, the clock is shut down so that instructions cannot be executed. There is no support in the specification for allowing the clock to continue to run during a frequency change. Dkt. No. 50 at 14–16.

In addition to the claims themselves, Defendant cites the following intrinsic and extrinsic evidence to support its position: Intrinsic evidence: ’708 Patent col.6 ll.26–67; ’708 Patent File Wrapper June 29, 2007 Amendment and Response at 12 (Defendant’s Ex. F, Dkt. No. 50-7 at 13); ’627 Patent File Wrapper November 7, 2012 Response at 11 (Defendant’s Ex. E, Dkt. No. 50-6 at 12). Extrinsic evidence: Thornton Decl. ¶ 87 (Defendant’s Ex. H, Dkt. No. 50-9 at 34–35).

Plaintiff replies: These terms are distinct from the Shutting-Down-the-Clocks-in-Response to-a-Frequency-Change-Initiation terms. In these terms, there is no support for limiting the “clocks”to “core clocks” or requiring the cessation of execution of instructions for the entire time the frequency changes. Dkt. No. 53 at 11–12.

Plaintiff cites further intrinsic evidence to support its position: ’708 Patent File Wrapper June 29, 2007 Amendment and Response (Defendant’s Ex. F, Dkt. No. 50-7).

Analysis

There are three issues in dispute. First, whether stopping execution of instructions during a frequency change necessarily means stopping the core clock. It does not. Second, whether the “clock” that is expressly stopped according to the claims is necessarily the core clock. It is. Third, whether the clock / execution of instructions is necessarily stopped for the entire time the frequency is changed. It is not.

Stopping execution of instructions does not necessarily require stopping the processor clock. Each of these terms fall into one of two general categories. The first category recites stopping execution of instructions for a frequency change. For example, Claim 23 recites: “processing unit that operates at [] a frequency responsive to a clock signal… stopping execution of instructions in said processing unit … [and] while instruction execution is stopped, adjusting said programmable frequency generator to change the frequency.” The second category recites stopping the processor clock in order to stop execution of instructions. For example, Claim 25 of the ’708 Patent recites: “The method of claim 23 wherein said stopping comprises stopping said clock signal.” Thus, under the plain meaning of the claims, stopping execution of the instructions is distinct from stopping the clock. There is nothing in the intrinsic record to mandate that stopping execution necessarily requires stopping the processor clock. This is different from the execution of instructions during a voltage change discussed above, which the intrinsic record established requires operation of the processor clock. That executing instructions during a voltage change requires an operational processor clock does not mean that not executing instructions requires stopping the clock. While the embodiments described in the patents do in fact stop the clock for the frequency change, this is not enough to read a stopping-the-clock limitation into all claims directed to changing the frequency—especially considering that some claims express stopping the clock and others do not. See Phillips v. AWH Corp., 415 F.3d 1303, 1323 (Fed. Cir. 2005) (en banc) (“we have expressly rejected the contention that if a patent describes only a single embodiment, the claims of the patent must be construed as being limited to that embodiment”); Thorner v. Sony Comput. Entm’t Am. LLC, 669 F.3d 1362, 1366 (Fed. Cir. 2012) (“It is likewise not enough that the only embodiments, or all of the embodiments, contain a particular limitation. We do not read limitations from the specification into claims; we do not redefine words. Only the patentee can do that.”); SRI Int’l v. Matsushita Elec. Corp., 775 F.2d 1107, 1122 (Fed. Cir. 1985) (en banc) (“It is settled law that when a patent claim does not contain a certain limitation and another claim does, that limitation cannot be read into the former claim in determining either validity or infringement.”).

The “clock” expressly stopped in the claims is the “core clock.” The Court understands that the issues here are related to asserted Claims 6, 13, 19, and 22 of the ’708 Patent which each expressly require stopping the “clock.” Claim 6 states: “wherein the processor includes a clock and said changing said operating frequency further comprises: shutting down said clock.” Claim 13 states: “wherein said processor includes a clock and said changing the frequency of operation further comprises: shutting down said clock.” Claim 19, which depends from Claim 14, states: “wherein said causing adjustment comprises shutting down said clock.” Claim 22, which depends from Claim 20, states: “wherein said adjusting said programmable frequency generator comprises stopping said clock signal.” The clock or clock signal of Claims 6, 13, and 22 each expressly are the processor or processing-unit clock. For Claim 14, the clock is that provided to the ‘means for executing instructions” which the parties agree is the “processing unit 16” described in the patents. Dkt. No. 54-1 at 16–17, Agreed No. 1. Thus, as plainly stated, each clock of the claims at issue is the processor or processing-unit clock. As described above, this “processor clock” is the core clock. See also, ’061 Patent col.3 ll.20–26; ’061 Patent File Wrapper, August 3, 2004 Response at 16–17, Dkt. No. 50 12 at 17–18.

Neither the clock nor the execution of instructions is necessarily stopped for all frequency changes. The terms at issue are found in open-ended claims. Open-ended claims allow for unrecited structure or steps. See, e.g., In re Affinity Labs of Tex., LLC, 856 F.3d 902, 907 (Fed. Cir. 2017). Thus, while the claims require changing the frequency while execution of instructions is stopped (which may or may not mean the clock is stopped), the claims do not thereby necessarily preclude also changing the frequency while execution of instructions is not stopped.

Accordingly, the Court rejects Defendant’s proposals to limit the claims to require stopping the core clock in order to stop execution of instructions and to require that the execution and clock are stopped for all frequency changes. For the terms that do not include the term “clock,” the Court holds those terms to have their plain and ordinary meaning without the need for further construction. For the clock terms at issue in Claims 6, 13, 19, and 22 of the ’708 Patent, the Court hereby construes “clock” to mean “core clock” and holds that the terms otherwise have their plain and ordinary meaning without the need for further construction.

Case No. 2:18-cv-00192

Semcon IP v. Amazon.com, Inc.

CLAIM CONSTRUCTION MEMORANDUM OPINION AND ORDER

Claim Construction B

The Parties’ Positions

Plaintiff submits: The meaning of these terms is clear without construction. As the Court held in Huawei, changing the voltage while instructions are being executed does not require that the clock remain “operational at all times during the voltage change.” Dkt. No. 48 at 15.

In addition to the claims themselves, Plaintiff cites the following intrinsic and extrinsic evidence to support its position: Intrinsic evidence: ’061 Patent col.6 ll.16–29. Extrinsic evidence: Carbonell Decl.9 ¶¶ 42–46 (Plaintiff’s Ex. E, Dkt. No. 48-6 at 18–19); Thornton Decl. ¶¶ 58–60 (Plaintiff’s Ex. F, Dkt. No. 48-7 at 24–25).

Defendant responds: These terms need to be construed to clarify that the core clock of the processor is not stopped and instructions are executed “at least during some point in the period of time that the voltage is changing between a first and a second voltage.” This is the rationale underlying the Court’s holding in Huawei. This is distinct from a situation in which the clock is active and instructions are executed after the command to change the voltage and before the voltage actually begins to change, but the clock is not active and instructions are not executed while the voltage is actually changing. During prosecution of the ’061 Patent, the patentee distinguished the prior art on this point—the clock is active or instructions are executed at some point during an actual change in voltage. Dkt. No. 50 at 12–14.

In addition to the claims themselves, Defendant cites the following intrinsic and extrinsic evidence to support its position: Intrinsic evidence: ’061 Patent File Wrapper August 3, 2004 Amendment and Response at 16–17 (Defendant’s Ex. K, Dkt. No. 50-12 at 17–18), September 15, 2005 Reasons for Allowance at 2 (Defendant’s Ex. C, Dkt. No. 50-4 at 6), March 6, 2006 Reasons for Allowance at 2 (Defendant’s Ex. A, Dkt. No. 50-2 at 6); ’708 Patent File Wrapper August 2, 2007 Reasons for Allowance at 2 (Defendant’s Ex. B, Dkt. No. 50-3 at 6). Extrinsic evidence: Thornton Decl. ¶ 59 (Defendant’s Ex. H, Dkt. No. 50-9 at 24–25).

Plaintiff replies: The Court did not hold in Huawei that the “core clock” must be functional at some point during a voltage change. This is important because while execution of instructions may require operation of a clock, it does not necessarily require operation of the core clock. Further, the patents do not distinguish between the point at which the voltage change is caused and the point at which the voltage actually changes. Dkt. No. 53 at 7–8.

Analysis

The main issue in dispute is whether the claimed execution of instructions during a voltage change necessarily requires operation of the “core clock.” It does.

To begin, the construction in Huawei was directed to resolving the dispute over whether the clock must run at all times during a voltage change. Huawei, 2017 U.S. Dist. LEXIS 108040, at *37. The Court there held that while “the clock is necessarily operational at least at some point during the voltage change” it is not “not necessarily … operational at all times during the voltage change.” Id. at *37–40. That is, in order to execute instructions, or to be able to execute instructions,10 during the voltage change the clock must be operational at some point during the voltage change. Id. The Court held that this is the plain meaning of the terms. The Court reiterates that holding here and further clarifies that the plain meaning of “changing the … voltage” and similar constructs is that the voltage change is actual, not simply requested or initiated or otherwise desired but not realized. The issue of which clock is used for executing instructions was not before the Court in Huawei.

In the Asserted Patents, the “core clock” must be enabled for a processor to be capable of executing instructions during the voltage change. For example, the patents provide:

The [frequency] generator 17 responds to values furnished by control software executing on the processor to produce from the slow clock a core clock for operation of the processing unit 16, one or more clocks for operation of the various system memory components shown as system memory 14 in the figure, the system bus, and any other components which might utilize[] a separate clock.

’061 Patent col.3 ll.20–23 (emphasis added). From this, the Court understands that the processor/processing-unit clock is the core clock. The patents further provide ways in which the processor voltage change will not disrupt the frequency generator so the instructions may be executed while the voltage is changing:

For example, if increases of approximately 50 millivolts are enabled, then the frequency generator will remain stable during the voltage increase and a system reset will not occur. This offers the advantage that the processor may continue to execute commands during the period in which the voltage change is taking place.

Id. at col.6 ll.24–29. From this, the Court understands that the processor is able to execute instructions during a voltage change because the core clock continues to operate during a voltage change. In contrast, the processor is shut down by shutting down the core clock for a frequency change. Id. at col.6 ll.32 – col.7 l.5 (“operations of the processor are prepared for shut down,” and the “sequencer … shut[s] down the core clock”). If the processor is able to execute commands during the voltage change based on other clocks, like the slow clock used by the generator to produce the core clock, the “advantage” of proceeding with a voltage change so as to not disrupt the frequency generator is illusory and the need to shut down operations of the processor for a frequency change is nonsensical. Further, the patents provide using an external clock for purposes other than continued execution of instructions during the voltage change but describe execution of instructions solely with respect to the core clock. See, e.g., id. at col.6 l.61–63.

The continued operation of the core clock to enable execution of instructions during the voltage change is ostensibly a point of novelty for the Asserted Patents. During prosecution of the ’061 Patent, the patentee explained that “executing instructions …while changing voltage …” means “instructions … are clocked through a computer processor while changing the voltage.” ’061 Patent File Wrapper, August 3, 2004 Response at 16, Dkt. No. 50-12 at 17. This was a distinction over the prior art because the prior art disclosed that the “voltage change … occur[s] when the processor clock … is not running” and “[t]he processor cannot execute instructions while the processor clock is not running.” Id. at 17 (emphasis added), Dkt. No. 50-12 at 18. The patent examiner noted this distinction over the prior art in granting the ’061 and ’708 Patents. ’061 Patent File Wrapper March 6, 2006 Reasons for Allowance at 2 (“the processor does not stop the clock”), Dkt. No. 50-2 at 6; ’708 Patent Filer Wrapper August 2, 2007 Reasons for Allowance at 2 (“the processor is not suspended from executing instructions … meaning that the processor does not stop the clock”), Dkt. No. 50-3 at 6. Ultimately, the Court understands “executing instructions” during a voltage change refers to using the core clock to clock instructions through the processor. The processor of the claims is able to execute instructions during a voltage change because the core clock is enabled.

The Court rejects Defendant’s proposed construction, however. First, the proposed construction requires the processor to “not stop the core clock … and continue[] execution of instructions in the period of time that the voltage is changing.” While the Court understands that Defendant is not advocating that the clock is enabled at all times during a voltage change, Dkt. No. 50 at 13–14, its proposed construction seems to say just that. Second, some claims require only the ability to execute instructions while others require actual execution of instructions. For example, Claim 1 of the ’061 Patent recites “executing instructions in said computer processor while changing the voltage” and Claim 26 of the ’708 Patent recites “changing the operating voltage from a first voltage to a second voltage while the processing unit is enabled to execute instructions.”

Accordingly, the Court hereby construes these voltage-change terms by construing “executing instructions” and variants in those terms in the claims at issue as follows:

• “executing … instructions” means “executing … instructions using the core clock”;

• “execution of … instructions” means “execution of … instructions using the core clock”;

• “execute instructions” means “execute instructions using the core clock”; and

• “executes … instructions” means “executes … instructions using the core clock.”

Case No. 2:18-cv-00192