Semcon IP v. Amazon.com, Inc.

CLAIM CONSTRUCTION MEMORANDUM OPINION AND ORDER

Claim Construction E

The Parties’ Positions

Plaintiff submits: The specific operating conditions listed in Defendant’s proposed construction are exemplary conditions described in the Asserted Patents. As exemplary embodiments, they should not be read into the claims. Dkt. No. 48 at 16.

In addition to the claims themselves, Plaintiff cites the following intrinsic and extrinsic evidence to support its position: Intrinsic evidence: ’061 Patent col.5 ll.21–29. Extrinsic evidence: Carbonell Decl. ¶¶ 47–50 (Plaintiff’s Ex. E, Dkt. No. 48-6 at 19–20).

Defendant responds: The operating conditions or characteristics of the claims are limited to those described in the Asserted Patents: operating frequency, operating voltage, operating temperature, and time the processor spends in an idle state. Specifically, the conditions do not include “instructions to be executed by the processor.” Such instructions were disclaimed as operating conditions during prosecution of the ’061 Patent. A “plain meaning” construction threatens to improperly allow operating conditions or characteristics to encompass instructions to be executed. Dkt. No. 50 at 16–18.

In addition to the claims themselves, Defendant cites the following intrinsic evidence to support its position: ’061 Patent col.2 l.67 – col.3 l.12; ’061 Patent File Wrapper September 8, 2008 Reply to Action Closing Prosecution in Inter Partes Reexamination at 2 (Defendant’s Ex. D, Dkt. No. 50-5 at 7).

Plaintiff replies: The patentee did not disclaim instructions to be executed from the scope of operating conditions. Rather, the patentee amended certain claims to include that a determination is made “independently of instructions to be executed by the processor.” This means that “instructions to be executed” are actually within the scope of “operating conditions,” else there would have been no need to amend the claims. Dkt. No. 53 at 8.

Analysis

There are two issues in dispute. First, whether the recited operating “conditions,” “characteristics,” and “parameters” of the processor are limited to those listed in the Asserted Patents. They are not. Second, whether the recited operating “conditions,” “characteristics,” and “parameters” of the processor necessarily excludes “instructions to be executed by the processor.” They do not.

The Asserted Patents’ list of operating conditions, namely, “the present frequency and voltage of operation, the temperature of operation, the amount of time the processor spends in one of what may be a number of idle states in which various components of the system are quiescent,” ’061 Patent col.5 ll.23–28, is not exhaustive. “[V]oltage and frequency monitoring” is expressly exemplary, id. at col.3 ll.2–5 (using “such as” to introduce voltage and frequency monitoring), as is monitoring of “temperature data.” Id. at col.3 ll.5–9 (using “e.g.” to introduce temperature data). Other exemplary condition monitoring includes “detecting other operations of the system including commands to be executed from which a particular type of operation to be executed may be determined.” Id. at col.3 ll.9–12 (using “including” to introduce a list of other operations detected). The patents also refer to “various operating characteristics” with reference to U.S. Patent App. No. 09/417,930. Id. at col.3 ll.12–15. Further, the patents disclose monitoring “various conditions of the processor that relate to power expenditure by the processor” which “may include …the amount of time the processor spends in one of what may be a number of idle states in which various components of the system are quiescent.” Id. at col.5 ll.21–28. Relatedly, the patents mention ramping up the frequency and voltage for a “short time,” suggesting the time of overclocking may also be an operating condition that is monitored. See id. at col.7 ll.45–58; Carbonell Decl. ¶ 49, Dkt. No. 48-6 at 20. Ultimately, the listed operating conditions/characteristics/parameters are not exhaustive as Defendant suggests.

Except as expressly provided in the claims, the “instructions to be executed by the” processor/processing device condition is not excluded from the claimed operating conditions/characteristics/parameters. Claim 1 of the ’247 Patent recites: “determining a level of permitted power consumption by a processing device from a set of operating conditions of the processing device, with the determining the level of permitted power consumption not based upon instructions to be executed by the processing device.” This expressly states that the “instructions to be executed by the processing device” are not part of the “operating conditions” used in “the determining [a] level of permitted power.” This suggests that “operating conditions” does not inherently exclude “instructions to be executed by the processing device.” Further, amending Claim 1 during prosecution of the ’061 Patent reexamination to expressly remove “instructions to be executed by the processor” from the conditions used in determining a reduced maximum power consumption level is not a broad disclaimer of “instructions to be executed by the” processor/processing device from the scope of “operating conditions” regardless of the role of those conditions in a claim.

Accordingly, the Court rejects Defendant’s proposal to limit the terms to “the present frequency and voltage of operation of the processor, the temperature of operation of the processor, or the amount of time the processor spends in one of what may be a number of idle states” and to necessarily exclude “instructions to be executed by the processor.” The Court hereby holds that the Operating-Conditions terms have their plain and ordinary meanings without the need for further construction.

Case No. 2:18-cv-00192

Semcon IP v. Amazon.com, Inc.

CLAIM CONSTRUCTION MEMORANDUM OPINION AND ORDER

Claim Construction D

The Parties’ Positions

Plaintiff submits: The plain meanings of these terms do not require that execution of instructions be stopped. Such a limitation is expressed in other claims and should not be read into Claims 1, 10, or 16 of the ’627 Patent. Further, while the terms require that clocks to the processing unit be “shut down,” other clocks may still operate and be received by the processing unit. Dkt. No. 48 at 22–23.

In addition to the claims themselves, Plaintiff cites the following extrinsic evidence to support its position: Carbonell Decl. ¶ 63 (Plaintiff’s Ex. E, Dkt. No. 48-6 at 24–25); Thornton Decl. ¶¶ 87–88 (Plaintiff’s Ex. F, Dkt. No. 48-7 at 34–36).

Defendant responds: See the Changing-the-Frequency-While-Execution-of-Instructions-is-Stopped Terms addressed above.

Plaintiff replies: Neither the ’627 Patent nor the prosecution history justify requiring shutting down the “core clock” or ceasing the execution of instructions. Dkt. No. 53 at 12.

Analysis

There are three issues in dispute. First, whether the processor “clocks” shut down in the claims necessarily include the “core clock.” They do. Second, whether shutting down the processor clock necessarily means that there are no instructions executed. It does not. Third, whether the clock is necessarily stopped for the entire time the frequency is changed. It is not.

The “clocks” of the claims at issue, Claims 1, 10, and 16 of the ’627 Patent, include the core clock. Claim 1 of the ’627 Patent recites:

a frequency generator configured to receive a first clock signal from a clock generator and to adjust a frequency of said first clock signal to furnish clock signals at different frequencies to said processing unit and said second component … wherein, in response to initiating a change in frequency for said processing unit, said processing unit is configured to start a counter and to shut down clocks to said processing unit and said second component.

Claim 10 similarly recites:

said frequency generator configured to adjust said frequency of said first clock signal to concurrently furnish clock signals at different frequencies to said processing unit and said second component … wherein, in response to initiating said change in frequency, said processing unit is configured to start a counter and to shut down clocks to said processing unit and said second component.

Claim 16 similarly recites:

a first clock signal at a first frequency to provide a second clock signal at a second frequency to a processing unit … in response to initiation of a change in frequency for said processing unit, starting a counter and stopping said first and second clock signals.

That is, the “clocks” or “clock signals” of the claims expressly include the processing-unit clock. As explained above, the processing-unit clock is the core clock. See also, ’061 Patent col.3 ll.20–26; ’061 Patent File Wrapper, August 3, 2004 Response at 16–17, Dkt. No. 50-12 at 17–18.

While, as set forth above, the Court understands that execution of instructions during a voltage change requires operation of the core clock, it does not understand the claims at issue here to preclude instructions based on other clocks. As set forth above, the patentee explained during prosecution of the ’061 Patent that execution of instructions during the voltage change means clocking instructions through the processor and that this is not possible when the processor clock is not running. ’061 Patent File Wrapper, August 3, 2004 Response at 16–17, Dkt. No. 50 12 at 17–18. Thus, claimed execution of instructions during the voltage change requires operation of the core clock. The claims at issue here, however, do not refer to either continuing to execute instructions or stopping the execution of instructions, during a voltage change or otherwise. Nor do the claims, which are open-ended, preclude the use or presence of unrecited clocks. Ultimately, the Court finds nothing in the intrinsic record to require that any and all instructions be executed only through use of the core clock. While the Court also finds no intrinsic-record disclosure of using any clock other than the core clock to execute instructions, whether such is technically possible is an issue of fact outside the patents and whether a claim to such undisclosed clock is supported by the disclosure of the Asserted Patents is an issue of invalidity under the enablement or written-description requirements, not an issue of claim construction. Phillips v. AWH Corp., 415 F.3d 1303, 1327 (Fed. Cir. 2005) (en banc) (“we have certainly not endorsed a regime in which validity analysis is a regular component of claim construction”).

The terms at issue do not require that the clocks are necessarily shut down for the entire frequency-change operation. The claims themselves recite when the shut-down clocks are reenabled. For instance, Claim 10 recites:

processing unit configured to register a value corresponding to an amount of time allowed for phase-locked-loop (PLL) circuitry to lock in response to a change in frequency of said first clock signal … a frequency generator coupled to said clock generator and comprising said PLL circuitry, said frequency generator configured to adjust said frequency of said first clock signal to concurrently furnish clock signals at different frequencies to said processing unit and said second component … in response to initiating said change in frequency, said processing unit is configured to start a counter and to shut down clocks to said processing unit and second component … in response to said counter reaching said value, said processing unit is configured to tum on said clocks.

The claim expressly recites that the clocks are shut down for a sufficient period of time to allow the phase-locked-loop circuitry to lock in in response to a change in frequency. Claims 1 and 16 are different. Claim 1 recites: “in response to said counter reaching a specified value, said processing unit is configured to turn on said clocks.” Claim 16 recites: “in response to said counter reaching a specified value, restarting said first and second clock signals.” Unlike Claim 10, Claims 1 and 16 are silent on how or whether the “specified value” is related to the duration of the frequency change. While the Court finds no intrinsic-record disclosure of a specified value other than one “used to measure the time allowed for the phase-lock-loop circuitry to lock to the new frequency,” ’061 Patent col.6 ll.63–66, whether the disclosure of the Asserted Patents supports a claim to such is an issue of invalidity under the enablement or written-description requirements, not an issue of claim construction. Ultimately, the Court finds nothing in the intrinsic record that mandates the clocks be shut down for the entirety of the frequency change.

Accordingly, the Court rejects Defendant’s proposals to limit the claims to prohibit execution of instructions other than those enabled by the core clock and to limit the claims to prohibit an enabled core clock at any point during a frequency-change operation. The Court hereby construes the “clock signal” terms as set forth below, and holds that the shutting-down-the-clocks-in-response-to-a-frequency-change-initiation terms otherwise have their plain and ordinary meaning without the need for further construction:

• In Claims 1 and 10 of the ’627 Patent, “in response to initiating [a/said] change in frequency … shut down clocks to said processing unit and said second component” means “in response to initiating [a/said] change in frequency … shut down clocks, including the core clock, to said processing unit and said second component”; and

• In Claim 16 of the ’627 Patent, “in response to initiation of a change in frequency for said processing unit … stopping said first and second clock signals” means “in response to initiation of a change in frequency for said processing unit … stopping said first and second clock signals, including the core clock.”

Case No. 2:18-cv-00192

Semcon IP v. Amazon.com, Inc.

CLAIM CONSTRUCTION MEMORANDUM OPINION AND ORDER

Claim Construction C

The Parties’ Positions

Plaintiff submits: These terms are not limited to require either stopping the core clock or cessation of execution of instructions at all times while the frequency is changing. With respect to stopping the core clock, dependent Claim 6 of the ’708 Patent expressly requires “shutting down said clock.” This means that the frequency change recited in Claim 1, from which Claim 6 depends, does not require shutting down the clock.With respect to whether the claims allow for a frequency change while executing instructions, the claims are open ended and it would be improper to read such a negative limitation into a positive requirement for frequency change while execution is stopped. Dkt. No. 48 at 21–22.

In addition to the claims themselves, Plaintiff cites the following extrinsic evidence to support its position: Carbonell Decl. ¶¶ 61–65 (Plaintiff’s Ex. E, Dkt. No. 48-6 at 24–25).

Defendant responds: The intrinsic record is clear that the core clock and execution of instructions are both stopped for a frequency change. As explained in the Asserted Patents, the clock is shut down so that instructions cannot be executed. There is no support in the specification for allowing the clock to continue to run during a frequency change. Dkt. No. 50 at 14–16.

In addition to the claims themselves, Defendant cites the following intrinsic and extrinsic evidence to support its position: Intrinsic evidence: ’708 Patent col.6 ll.26–67; ’708 Patent File Wrapper June 29, 2007 Amendment and Response at 12 (Defendant’s Ex. F, Dkt. No. 50-7 at 13); ’627 Patent File Wrapper November 7, 2012 Response at 11 (Defendant’s Ex. E, Dkt. No. 50-6 at 12). Extrinsic evidence: Thornton Decl. ¶ 87 (Defendant’s Ex. H, Dkt. No. 50-9 at 34–35).

Plaintiff replies: These terms are distinct from the Shutting-Down-the-Clocks-in-Response to-a-Frequency-Change-Initiation terms. In these terms, there is no support for limiting the “clocks”to “core clocks” or requiring the cessation of execution of instructions for the entire time the frequency changes. Dkt. No. 53 at 11–12.

Plaintiff cites further intrinsic evidence to support its position: ’708 Patent File Wrapper June 29, 2007 Amendment and Response (Defendant’s Ex. F, Dkt. No. 50-7).

Analysis

There are three issues in dispute. First, whether stopping execution of instructions during a frequency change necessarily means stopping the core clock. It does not. Second, whether the “clock” that is expressly stopped according to the claims is necessarily the core clock. It is. Third, whether the clock / execution of instructions is necessarily stopped for the entire time the frequency is changed. It is not.

Stopping execution of instructions does not necessarily require stopping the processor clock. Each of these terms fall into one of two general categories. The first category recites stopping execution of instructions for a frequency change. For example, Claim 23 recites: “processing unit that operates at [] a frequency responsive to a clock signal… stopping execution of instructions in said processing unit … [and] while instruction execution is stopped, adjusting said programmable frequency generator to change the frequency.” The second category recites stopping the processor clock in order to stop execution of instructions. For example, Claim 25 of the ’708 Patent recites: “The method of claim 23 wherein said stopping comprises stopping said clock signal.” Thus, under the plain meaning of the claims, stopping execution of the instructions is distinct from stopping the clock. There is nothing in the intrinsic record to mandate that stopping execution necessarily requires stopping the processor clock. This is different from the execution of instructions during a voltage change discussed above, which the intrinsic record established requires operation of the processor clock. That executing instructions during a voltage change requires an operational processor clock does not mean that not executing instructions requires stopping the clock. While the embodiments described in the patents do in fact stop the clock for the frequency change, this is not enough to read a stopping-the-clock limitation into all claims directed to changing the frequency—especially considering that some claims express stopping the clock and others do not. See Phillips v. AWH Corp., 415 F.3d 1303, 1323 (Fed. Cir. 2005) (en banc) (“we have expressly rejected the contention that if a patent describes only a single embodiment, the claims of the patent must be construed as being limited to that embodiment”); Thorner v. Sony Comput. Entm’t Am. LLC, 669 F.3d 1362, 1366 (Fed. Cir. 2012) (“It is likewise not enough that the only embodiments, or all of the embodiments, contain a particular limitation. We do not read limitations from the specification into claims; we do not redefine words. Only the patentee can do that.”); SRI Int’l v. Matsushita Elec. Corp., 775 F.2d 1107, 1122 (Fed. Cir. 1985) (en banc) (“It is settled law that when a patent claim does not contain a certain limitation and another claim does, that limitation cannot be read into the former claim in determining either validity or infringement.”).

The “clock” expressly stopped in the claims is the “core clock.” The Court understands that the issues here are related to asserted Claims 6, 13, 19, and 22 of the ’708 Patent which each expressly require stopping the “clock.” Claim 6 states: “wherein the processor includes a clock and said changing said operating frequency further comprises: shutting down said clock.” Claim 13 states: “wherein said processor includes a clock and said changing the frequency of operation further comprises: shutting down said clock.” Claim 19, which depends from Claim 14, states: “wherein said causing adjustment comprises shutting down said clock.” Claim 22, which depends from Claim 20, states: “wherein said adjusting said programmable frequency generator comprises stopping said clock signal.” The clock or clock signal of Claims 6, 13, and 22 each expressly are the processor or processing-unit clock. For Claim 14, the clock is that provided to the ‘means for executing instructions” which the parties agree is the “processing unit 16” described in the patents. Dkt. No. 54-1 at 16–17, Agreed No. 1. Thus, as plainly stated, each clock of the claims at issue is the processor or processing-unit clock. As described above, this “processor clock” is the core clock. See also, ’061 Patent col.3 ll.20–26; ’061 Patent File Wrapper, August 3, 2004 Response at 16–17, Dkt. No. 50 12 at 17–18.

Neither the clock nor the execution of instructions is necessarily stopped for all frequency changes. The terms at issue are found in open-ended claims. Open-ended claims allow for unrecited structure or steps. See, e.g., In re Affinity Labs of Tex., LLC, 856 F.3d 902, 907 (Fed. Cir. 2017). Thus, while the claims require changing the frequency while execution of instructions is stopped (which may or may not mean the clock is stopped), the claims do not thereby necessarily preclude also changing the frequency while execution of instructions is not stopped.

Accordingly, the Court rejects Defendant’s proposals to limit the claims to require stopping the core clock in order to stop execution of instructions and to require that the execution and clock are stopped for all frequency changes. For the terms that do not include the term “clock,” the Court holds those terms to have their plain and ordinary meaning without the need for further construction. For the clock terms at issue in Claims 6, 13, 19, and 22 of the ’708 Patent, the Court hereby construes “clock” to mean “core clock” and holds that the terms otherwise have their plain and ordinary meaning without the need for further construction.

Case No. 2:18-cv-00192